Video Development System
The iVeia Video Development Kit provides a platform on which video or similar applications for the iVeia Processing Module may be developed. The iVeia Processing Module is ideal for video applications since the complex video co-processing occurs on the same board using the combined processing elements of an FPGA and processor.
The Development Kit contains an iVeia Processing Module and a GigaFlex I/O Module. The GigaFlex I/O Module connects high speed Camera Link to the iVeia Processing Module so that high-definition image digital data may be processed by the module.
iVeia’s Velocity-EHF™ development suite, libraries, and IP, simplify development of hybrid software and FPGA applications. The Velocity-EHF includes a simplified FPGA framework and software libraries for managing interfaces between the FPGA and the processor. iVeia’s Zero-copy Application Ports (ZAP) provide low-latency high-speed transfer of both in-band and out-of-band data between the user FPGA application and the software application. An Open Cores Protocol (OCP) master interface in the FPGA allows the user to implement custom peripherals or utilize iVeia’s (or other freely available) OCP cores and associated libraries. iVeia provides a memory-mapped OCP register bank and memory interfaces to simplify the user FPGA design. For users unfamiliar with FPGA design, iVeia provides turn-key FPGA designs that abstract the FPGA from the software application.
| Product | GPP | FPGA | DSP Capability | Memory | High-Speed I/O | Video GigaFlex I/O Option | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| Technology | Max Speed | Technology | Denisty | Technology | Max Speed | Product | Camera Link | |||
| Titan-v5e | Xilinx PPC (Single PPC440) | Xilinx Virtex-5 | FX70T or SX50T | Up to 384MB DDR2 SDRAM | 2x GigE, or Custom | GigaFlex CL2-b | 2x Base Input or Output 1x Med/Full Input or Output (Optional) | |||
| Titan-V5x | Xilinx PPC (Dual PPC440) | Dual, Up to 450 MHz | Xilinx Virtex-5 | FX100T or SX95T | Up to 2GB DDR2 Configurable | 6 GTX: 2x GigE and 4x PCIe 1.1, or Custom | GigaFlex CL2-b | 2x Base Input or Output 1x Med/Full Input or Output (Optional) | ||
| Atlas-I-LPe | TI OMAP 3530/DM3730 (ARM Cortex-A8) | UP to 1.0 GHz | Xilinx Spartan-6 | Up to LX45 | TI C64x Core, ARM NEON Extensions | 800 MHz | Up to 1GB LPDDR | Optional GigE (RGMII) | Breckenridge | 2x Base Input or Output 1x Med/Full Input or Output (Optional) |
| Atlas-I-Z7e | Xilinx (Dual, ARM Cortex-A9) | Dual, up to 800 MHz | Xilinx Zynq-7000 EPP | 7020 | Up to 1GB LPDDR | Optional GigE (RGMII) | Breckenridge | 2x Base Input or Output 1x Med/Full Input or Output (Optional) | ||
| Atlas-II-V5x | Xilinx PPC (Dual PPC440) | Dual, Up to 450 MHz | Xilinx Virtex-5 | FX100T or SX95T | Up to 2GB DDR2 Configurable | 6 GTX: 2x GigE and 4x PCIe 1.1, or Custom | GigaFlex CL2-b | 2x Base Input or Output 1x Med/Full Input or Output (Optional) | ||
