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iScale-DSP FAQ

Q: Is iScale-DSP code compatible with other DSPs?

A: The iScale-DSP was designed as a co-processor and, by itself, does not contain the test-and-branch/decision logic that would be required of a C-compatible processor. However, the hardened PowerPC processors of the Virtex FX FPGAs perform these functions extremely efficiently (and with no logic consumption). By combining the PowerPC and the iScale-DSP iVeia has created a practical DSP implementation in an FPGA, but at the expense of pure code compatibility.

Q: How is the iScale-DSP programmed?

A: Initially, iVeia will provide blocking and non-blocking C library functions for the PowerPC that setup and execute common DSP operations on the iScale-DSP. This will allow the user to develop in C on the PowerPC and then off-load (using the inline library functions) the processor-intensive portions of the code to the iScale-DSP. Future versions will allow the user to program the iScale-DSP using a scripting language similar to MATLAB. Since the iScale-DSP performs large-scale matrix functions very well, MATLAB users will find the iScale-DSP intuitive to program.

Q: What are the expected DMIPS?

A: The performance is dependent on how large you scale the ALU, which is configurable. DMIPS isn't applicable since it is an array processor (one instruction could perform on millions of points of data). However, benchmarks for FIR and FFT functions will demonstrate performance comparable to TI 64XX for smaller point operations (less than 16K) but for large operations much better performance numbers.

Q: What are expected clock speeds for both internal to the DSP core and external to the part?

A: The internal clocks and external memory clocks are asynchronous. The iScale-DSP can run greater than 250 MHz in a Virtex-5 FXT with a -1 speed grade, and supports DDR2-500 for external memory.

Q: What are the cache sizes for the core?

A: Cache sizes are configurable. There are four caches (one for each bus) that are implemented in block RAM.

Q: How much logic is consumed by the DSP core?

A: A mid-sized implementation of an iScale-DSP will fit into less than 30% of an Virtex-5 FX70T. Scaling the core mostly impacts the use of DSP48 tiles and BRAMS. In combination with the Velocity-SoC (PowerPC architecture), iVeia can provide a high-performance single-chip signal processing architecture in less than 50% of the Virtex-5 FX70T.

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