IP Cores and Software
Heterogeneous Computing. Simplified.
Velocity-EHF™: Portability and Abstraction for Heterogeneous Architectures
The Velocity Embedded Hybrid Framework (Velocity-EHF) provides an application framework and portability layer for embedded hybrid computing platforms, specifically, mixed microprocessor and programmable logic compute platforms. Just as an operating system provides a common well-defined framework for software applications, the Velocity-EHF extends that concept to include programmable logic.
The Velocity-EHF provides standard interfaces for both software and programmable logic applications and consists of a suite of programmable logic IP blocks and software libraries that are combined to form a framework specifically suited for embedded hybrid computing (or heterogeneous computing) platforms and applications. The programmable logic interfaces simplify design without sacrificing performance or over consuming programmable logic resources (most instantiations consume less than ten percent of the logic). The software libraries and device drivers provide simplified high-speed transfer to/from programmable logic using direct memory access as well as simplified control plane functions, such as configuration, control, and status of the programmable logic application.
Besides application portability, one of the key benefits of the Velocity-EHF is that it creates a natural partition between the programmable logic development and the software development, thereby allowing software and hardware teams to develop independently without the need for multiple integration stages.
Just as a Linux Board Support Package (BSP) provides a software portability layer between different Linux hardware, the Velocity-EHF creates such a layer for both software and programmable logic. iVeia ports the Velocity-EHF framework to each one of its hybrid computing modules (most all of them), and even some vendor-specific development kits. In doing so, this allows a user to port their applications from one module to another with very little or almost no additional effort, even if the module utilizes a substantially different underlying technology.
This is a powerful feature since iVeia’s processor modules are also form-factor and electrically compatible within product families (the Atlas family, for instance). The combination of soft and hard portability allows a designer to quickly address market needs by being able to seamlessly upgrade their product hardware (to add features/performance) or even downgrade (to save power/cost).
Velocity-VIP™: Video and Image Processing
The Velocity-VIP is a video and image processing software library and IP core repository that includes the basic building blocks required for many video processing applications. iVeia’s core libraries take full advantage of the heterogenous architecture, utilizing the processor to provide flexible run-time configuration and improved resource efficiency over standard IP cores.
The Velocity-VIP library includes the following cores:
- Video 2D Convolution
- Video Average Operation
- GigE Vision Camera Interface
- BT656 Encoder
- BT656 Decoder
- Camera Link Base, Medium, and Full
- Camera Link Calibration
- Colorspace Conversion
- Video Close Operation
- Video Open Operation
- Video Erode Operation
- Video Horizontal and Vertical Delay
- Video Dilate Operation
- HDMI/DVI Timing Generator
- Video Re-time Operation
- Video Sobel Edge Detection
- Video Guassian Edge Detection
- HDMI/DVI Interface
- Video Crop/Resize
- Video Erode Operation
- N-Port External Video Frame Buffer Interface
- Frame Buffer Input Interface
- Frame Buffer Output Interface
- Multi-Frame Video FIFO
- Harris Corner Operation
- User-Defined 2D Kernel Operation
- Buffers video lines for vertical operations
- Video Non-Maxima Suppression
- Video Signal Multiplexer
- Video Fusion Operation
- Video Timing Generator
- Video Snapshot Utility
Velocity-SDR™: Software-Defined Radio and General-Purpose Signal Processing
The Velocity-SDR is a signal processing software library and IP core repository that includes the basic building blocks required for many software-defined radio and similar signal processing applications. iVeia’s core libraries take full advantage of the heterogenous architecture, utilizing the processor to provide flexible run-time configuration and improved resource efficiency over standard IP cores. Parameters such as coefficients, decimation/interpolation rates, scale factors, etc… can be calculated by the processor and uploaded to the IP core in real-time.
The Velocity-SDR library includes the following cores:
- Digital-Down Converter (DDC)
- Digital-Up Converter (DUC)
- Polyphase Filter Bank
- Compact Finite-Impulse Response Filter (FIR)
- Programmable Direct Digital Synthesizer (DDS)
- Deep Signal Buffer with Trigger
- Cascaded Integrator-Comb Filter (CIC)
- Fixed-point Multiply-Accumulate Function (MAC)
- Fixed-point Saturate/Round Operation
- Data Packetize/Timestamp
- Deep Signal Pipeline Delay and Rewind
Velocity-PDE™: Integrated Development for iVeia SoMs and Velocity IP
The Velocity Platform Development Environment (Velocity-PDE) provides a unified vendor-agnostic development flow for both software and FPGA designs. It includes utilities for rapid project creation and migration, framework generation and build tools, platform cross-compilers, libraries, platform IP cores and example source code.
Interface IP Cores
iVeia has developed a number of IP cores to interface programmable logic devices to a variety of peripherals and I/O:
- N-Port External Memory Arbiter
- Camera Link
- GigE Vision
- 10 Gigabit Ethernet
- Linear Tech LVDS serial ADCs
- Texas Instruments LVDS serial ADCs
- Analog Devices LVDS serial ADCs and DACs
- MIPI CSI-2
- I2S for Audio
- BT656 for Analog Video
- A variety of LCDs and Touchscreens